//////////////////////////////////////////////////////////////////////////////////
// Company:        RIT
// Engineer:       Cody Cziesler, Nick Desaulniers
//
// Create Date:    10:58:44 04/07/2011
// Design Name:    Omicron
// Module Name:    omicron
// Project Name:   Pipelined CPU
// Target Devices: Xilinx Spartan-3E
// Tool versions:  Xilinx ISE Project Navigator
// Description:    This is a pipelined CPU with five stages: IF, ID, EX, M, WB
//
// Revision:
// Revision 0.01 - File Created
// Revision 1.00 - Fixed a semi-colon problem
// Revision 2.00 - Added cu_branch
// Revision 3.00 - Changed name of data_path pin "id_opcode_out" (CRC)
// Revision 4.00 - Changed cu_alu_opcode width
// Revision 5.00 - Added cu_branch wire declaration, removed cu_reg_dest (CRC)
// Revision 6.00 - Added mrst_n, a master reset, which takes the rdy signal from the clk_blk and ands it with the rst_n (CRC)
// Revision 7.00 - Removed mrst_n (KISS), changed cu_alu_opcode size (CRC)
// Revision 8.00 - Removed clk_blk from this level, moved to omicron_top (CRC)
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

`include "include.v"

module omicron(
  input wire        rst_n,
  input wire        clk,
  input wire        clk_n,
  output wire [7:0] leds
);

// Control Signals
wire [4:0]  cu_alu_opcode;
wire [3:0]  id_opcode;
wire [2:0]  id_function;
wire [1:0]  cu_branch;
wire        cu_reg_load;
wire        cu_alu_sel_b;
wire        cu_dm_wea;
wire        cu_reg_data_loc;

// Data Path
data_path i_data_path (
  .clk(clk),
  .clk_n(clk_n),
  .rst_n(rst_n),
  .cu_reg_load(cu_reg_load),
  .cu_alu_sel_b(cu_alu_sel_b),
  .cu_alu_opcode(cu_alu_opcode),
  .cu_dm_wea(cu_dm_wea),
  .cu_reg_data_loc(cu_reg_data_loc),
  .cu_branch(cu_branch),
  .id_opcode_out(id_opcode),
  .id_function_out(id_function),
  .leds(leds)
);


// Control Unit
control_unit i_control_unit (
    .clk(clk),
    .rst_n(rst_n),
    .id_opcode(id_opcode),
    .id_function(id_function),
    .cu_reg_load(cu_reg_load),         // RegLd
    .cu_alu_sel_b(cu_alu_sel_b),       // AluSelB
    .cu_alu_opcode(cu_alu_opcode),     // AluCtrl
    .cu_dm_wea(cu_dm_wea),             // MemWr
    .cu_reg_data_loc(cu_reg_data_loc), // AluOrMem
    .cu_branch(cu_branch)              // BrCtrl
);


endmodule
